While there are numerous field programmable gate array (FPGA)-based system offerings on the market today, there is no single accepted programming standard that facilitates using them. FPGAs are predominantly programmed with hardware description languages (HDLs) and conventional processors are programmed with modern high-level languages. In addition, the compilation and design flow for each of these targets are completely different. Programming FPGAs (hardware) requires the use of electronic design automation (EDA) toolflows that are complex and time consuming to synthesize the HDL into a circuit, whereas programming CPUs (software) enjoys the benefits of well established instruction set architectures (ISAs) and advanced compilers that offer a much simpler programming experience. The lack of (1) a single semantic programming domain, (2) standard FPGA device interfaces, and (3) an integrated toolflow for programming across the hardware-software boundary means the burden is largely on the programmer to manage the heterogeneous complexity.
A number of companies and products are focused on lowering the programming burden associated with FPGAs, but do not address the CPU/FPGA divide directly. Instead, their aim is to raise the programming abstractions offered by HDLs like VHDL and Verilog from the level of gates, muxes and flip-flops to be on par with modern high-level programming languages such as C/C++ and Java. In doing so, they offer the possibility for skilled software developers to design hardware through high-level synthesis: the compilation and synthesis of logic from high-level languages.
Despite many advances in high-level synthesis, programming FPGAs remains difficult, in part because the final integration of software and hardware is a challenge that the programmer bares. A typical off-the-shelf FPGA device is offered as a raw fabric with little or no infrastructural intellectual property (IP) (also referred to as service layer in this disclosure) to connect it to another device or component in a heterogeneous system. The term “IP” in hardware technology (and henceforth in this disclosure) is used to refer to a hardware design block with a well-defined interface and functionality.
There are several vendors that create custom FPGA boards with a highly tuned I/O infrastructure to support communication interfaces such as PCIe, and Ethernet and off-chip memory resources such as DDR-SDRAM, QDR-SRAM etc. The users can implement their applications either in HDL or using a high level synthesis framework and connect it with the infrastructure provided by the board vendor. This leads to a faster time-to-market as users can focus on developing their core application and the communication and storage infrastructure is provided by the board vendor. However, this prevents portability as the vendor infrastructure is often proprietary and created particularly for one board.